The invention relates in general to system architecture. More specifically, the invention relates to improving the performance of systems having a local bus and a global bus.
Advancements in semiconductor technology have enabled more cost effective computing and networking hardware architectures. Traditionally, system intelligence was centrally located within the computer or networking switch or router. Referring to FIG. 1a, computing or networking systems traditionally comprise a motherboard 101, a plurality of adapter cards 102a-d, all of which are communicatively coupled through a system backplane 103.
Motherboards 101 are the traditional location of a system""s intelligence. In the case of computing systems, the motherboard 101 is mostly responsible for running the operating system and application software. In the case of networking switches or routers, the motherboard 101 is responsible for identifying the destination address of each incoming traffic flow unit (such as a packet or cell). Computing system and router motherboards 101 are typically comprised of one or more microprocessors while switch motherboards 101 are typically comprised of application specific integrated circuits (ASICs).
In both computing and networking systems, traditionally, the adapter cards 102a-d may be viewed as having low levels of intelligence. That is, adapter cards 102a-d have traditionally been used for merely translating traffic flow between the motherboard 101 and various external connections 104a-d outside the system. In computing systems, the external connections may comprise the display (i.e., the computer screen), a Local Area Network (LAN) and speakers (e.g., for multimedia applications). In networking systems, the external connections 104a-d are typically a network.
In traditional systems, the intelligence is centrally located on the motherboard 101 because large semiconductor chips are needed to implement the intelligent functionality and its supporting logic. Thus implementing the system intelligence traditionally requires placing multiple large chips on the same card (the motherboard 101). Populating multiple large chips on a single card consumes significant board space, thus motherboards 101 tend to be large form factor cards. Adapter cards 102a-d are typically smaller form factor cards since they merely perform translation layer functionality. That is, adapter cards tend to comprise smaller semiconductor chips since their functionality is limited.
Pushing more intelligence onto the adapter card is typically prohibitive at traditional transistor integration levels since it involves placing large chips on each adapter card. The increased size of each adapter card 102a-d needed to accommodate computing or switching intelligence there, results in greater total boardspace consumption by the system as compared to a centralized, motherboard approach. However, increased transistor level integration levels has resulted in smaller chips for a fixed functionality or intelligence level. Thus, system level intelligence may now be pushed onto the adapter cards 102a-d themselves while maintaining cost effectiveness of the overall system. The result is a smaller system, as shown in FIG. 1b, that has no mother board and slightly larger adapter cards 105a-d. For networking systems, each adapter card 105a-d has the intelligence to route incoming/ingress traffic to the appropriate outgoing/egress adapter card 105a-d. 
A problem with implementing the intelligent adapter card architecture of FIG. 1b (particularly for multiport adapter cards) however, concerns managing the traffic flow between the connection 107a-d and the backplane 108. Specifically, the bandwidth associated with backplane 108 is typically higher than the bandwidth associated with the local routing capabilities of the adapter cards 105a-d. If designers do not account for these performance discrepancies (and integrate precautions into the intelligence of the adapter card), traffic units (such as packets, cells or words) may be dropped by the system at an unacceptably high rate.
Thus, what is needed is a system and method for overcoming the above described performance discrepancies.
An apparatus and method for providing a translation layer between a local bus and a global bus is described. The apparatus has a local bus and a global bus respectively coupled to a local bus gateway and a global bus gateway. A storage unit is coupled to both of the gateways, the storage unit having a traffic unit. Traffic control logic is coupled to at least one of the gateways and to at least one traffic statistic register.